The present invention relates to built-in self tests for on-chip circuit blocks, and more particularly, to configurations for built-in self tests for on-chip circuit blocks that reduce routing and die area.
Programmable logic devices (PLDs) are integrated circuits that can be configured to perform a variety of user functions. PLDs typically have numerous logic blocks that can be configured to implement various combinatorial and sequential functions. The logic blocks have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic blocks in almost any desired configuration.
PLDs usually have on-chip memory blocks. Each of the memory blocks contains an array of memory cells. The memory cells can be, for example, SRAM, DRAM, EPROM, EEPROM, or Flash EEPROM cells. The memory blocks are dispersed throughout the chip in between the logic blocks.
After a PLD is manufactured, the memory cells in the memory blocks must be tested to ensure that they are operating properly. In recent years, the number of memory cells in PLD chips has grown considerably. As the number of on-chip memory blocks in PLDs increases, it becomes increasingly difficult to test the memory blocks in a cost effective manner.
Usually on-chip memory is tested using build-in self test (BIST) controllers. BIST is a preferred technique for memory blocks that have a large number of memory cells. PLDs often have a huge number of small memory blocks that have 512 bits to 64K bits each. As a result, it is not cost effective to have separate on-chip BIST controllers for each memory block.
Another option is to place one BIST controller on the PLD and route test signals from the single BIST controller directly to all of the memory blocks. However, this techniques places a large demand on the PLD's interconnect structure. The same set of signals has to be routed to numerous on-chip memory blocks from one BIST controller along dedicated routing wires.
Another option is to program soft BIST controllers in programmable logic on a PLD. The BIST controllers are used for testing the memory blocks and then erased after testing is completed. There is no hardware overhead, and the existing programmable routing structure is programmed to route signals from the BIST controller to the memory blocks.
Once a particular design for a PLD has been successfully implemented and tested, the design may not need to be changed again. At that point, it may be desirable to reduce production costs by implementing the design in a lower cost mask-programmable PLD (MPLD). Altera's Hardcopy device is an example of a MPLD.
An MPLD is a device that is configured or “hard-wired” during the fabrication of the device. For example, the PLD manufacturer fabricates a MPLD design by using a specific mask corresponding to a user's design. The specific mask is chosen so that logic blocks and the interconnect structure are pre-programmed to perform the design.
Soft BIST controllers cannot be programmed into MPLDs to test on-chip memory blocks, because the functionality of the on-chip logic is fixed during manufacture. Therefore, additional hardware is required to implement BIST for memory blocks in MPLDs.
It is generally more efficient to have a dedicated BIST controller for a large memory block, because the relative hardware overhead is small. However, it is very expensive in terms of tester time and memory to run all the memory vectors from the tester. Also, getting enough pins to access all the memory blocks may be difficult to come by.
It is not cost effective to have an individual BIST controller for every memory block on an integrated circuit (IC) that has a large number of small memory blocks. On other hand, using one BIST controller that routes test signals directly it to hundreds of memory blocks all over an IC along dedicated routing wires causes routing congestion.
Therefore, it would be desirable to provide techniques for testing memory blocks and other circuit blocks on MPLDs and ASICs that minimize the amount of on-chip circuitry and dedicated routing resources needed to implement the tests.